Design Verification Engineer- San Francisco Bay Area, CA
Optical Interconnect, Data Centers, AI
Role Brief:
My client is looking for a Principal Design Verification Engineer to lead full chip/block level verification.
Responsibilities:
- Own verification plan for complex SoC with high-speed interfaces
- Define and implement verification infrastructure
- Implement testbenches & monitors using UVM
- Collaborate with world-class hardware/software architects, customers, and engineers to transform product vision
Skillset:
- 7+ years' verification experience
- Successful track record in verifying chips & designs
- Strong knowledge of UVM methodology
- Experience in high-speed memory highly desirable
- Python experience a big plus
This is an exciting opportunity to join an industry leading semiconductor company who already have some of the most exciting technologies on the market. If you are looking for a company that will provide you with career progression and offer an excellent compensation package, then this is the job for you.
Location:
San Francisco Bay area, CA
For immediate consideration please send your resume to tom.ridd@lumicity.io